IEEE Electron Device Letters · 2006 · 66 citations · 15 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsComplementary Metal-oxide-semiconductor TechnologyIii-v SemiconductorsMetal-oxide-semiconductor Field-effect TransistorsSemiconductor Device MaterialsSemiconductor HeterostructuresSemiconductor PhysicsChannel DopingEnhancement-mode TransistorsFermi LevelFermi Level PinningFermi SurfaceGate Oxide InterfacesGate OxidesHigh-electron-mobility Transistors
This letter introduces the first enhancement-mode GaAs n-channel MOSFETs with a high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The NMOSFETs feature an In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.3</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.7 </sub> As channel layer, a channel mobility of up to 6207 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots, and a dielectric stack thickness of 13.1-18.7 nm. Enhancement-mode NMOSFETs with a gate length of 1 mum, a source/drain spacing of 3 mum, and a threshold voltage of 0.05 V show a saturation current, transconductance, on-resistance, and subthreshold swing of 243 mA/mm, 81 mS/mm, 8.0 Omegamiddotmm, and 162 mV/dec, respectively
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Gallium arsenide MOS transistors
H.W. Becke, R. Mark Hall, J. White · Solid-State Electronics · 1965 · 97 citations