HPTR: Hardware partition in time redundancy technique for fault tolerance

Abstract

A fault-masking technique for both arithmetic and logical operations in an arithmetic logic unit (ALU) is proposed. The technique, which is basically time redundant, takes advantage of both time and hardware redundancy concepts. The method with which error correction is accomplished resembles that of triplication of hardware. Time redundancy is then used to complete the computation and obtain the final result on the same hardware. For example, a 12-b addition operation can be realized by using each of three 4-b adder modules three times in parallel. During each partial calculation, the error correction is accomplished by taking the majority gate of the results from the three 4-b adder blocks. The operation of an N-bit full-adder is shown as an example to describe the basis of the hardware partition in time redundancy (HPTR) technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>