Origin of the endurance degradation in the novel HfO<inf>2</inf>-based 1T ferroelectric non-volatile memories

Abstract

Novel HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based non-volatile ferroelectric field effect transistors (FeFETs) reveal integration and scaling properties superior to the devices utilizing perovskite-type ferroelectrics. However, until now the switching endurance of only 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> program/erase cycles could be proven. The mechanisms responsible for the cycling degradation have been scarcely studied so far. Therefore, the scope of this paper is to clarify the origin of the cycling degradation in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based FeFETs. Several possible degradation mechanisms - fatigue of the ferroelectric layer and degradation of the transistor gate stack - are proposed and investigated. The limited endurance properties were found to be linked to the transistor gate stack reliability rather than to the ferroelectric material itself. The gate leakage current measurements and the trapping analyses presented in this paper identified a degradation of the interfacial layer in the gate stack, which in turn is strongly linked to a reduction of ferroelectric memory window.