2004 · 19 citations · 9 references
Pocket ImplantElectrical EngineeringSemiconductor DeviceEngineeringVlsi DesignAdvanced Cmos TechnologyNanoelectronicsElectronic EngineeringBias Temperature InstabilityApplied PhysicsCmos TechnologyMosfet MismatchCmos Technologies EvolutionMicroelectronicsPocket Implant ImpactAdvanced 120
This paper deals with MOS transistors mismatch for advanced 120 nm and 90 nm CMOS technologies. In particular we demonstrate pocket implant impact on the gate contribution that becomes more and more important with the gate oxide thickness reduction. Such a phenomenon can appear as a limit for matching improvement with CMOS technologies evolution.
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Gate engineering for deep-submicron CMOS transistors
Bin Yu, Dong-Hyuk Ju, Wen‐Chin Lee et al. · IEEE Transactions on Electron Devices · 1998 · 77 citations