SOI design for competitive CMOS VLSI

Abstract

Device simulations using a physical SOI MOSFET model implemented in SPICE2 predict that properly designed silicon-on-insulator (SOI) has a substantial advantage over bulk CMOS VLSI with regard to hot-carrier-induced degradation. The simulations show that the (short-) n-channel SOI MOSFET, designed with moderately thin (not ultrathin) film having complete depletion in the film and at the back surface, and without an LDD region, will degrade much more slowly than a contemporary bulk MOSFET with an LDD. This suggests that the 5-V source can be retained for submicrometer SOI CMOS, whereas it must be lowered for bulk CMOS. The simulations and the optimal SOI designs they suggest are supported by measurements of thin-film and bulklike MOSFETs fabricated in SIMOX SOI.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>