Materials, Processes, and Performance of High-Wiring Density Buildup Substrate With Ultralow-Coefficient of Thermal Expansion

Abstract

Flip-chip bonding on organic sequential buildup substrate technology has been an essential part of semiconductor packaging. In the quest for an ever higher semiconductor performance, there has been a rapidly increasing need for a finer pitch area array of flip-chip joints. However, the pitch has been limited by packaging technology. An advanced buildup substrate for fine pitch flip-chip bonding has been developed to satisfy the requirements for the most advanced semiconductor devices. The advanced substrate features a low-coefficient of thermal expansion (CTE) of 3 ppm°C, a fine pattern of 8 μm in line width and spacing, micro-vias of 25 μm in diameter, and plated through-holes of 100 μm in pitch. These features accommodate the density of a chip I/O of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> , which is about ten times greater than that achieved in current organic packaging, and enable significant size reduction of semiconductor chips and the associated packages. The low-CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. This paper describes recent progress in the development of the advanced substrate technology as well as the technical difficulties.