A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 2<formula formulatype="inline"><tex Notation="TeX">$ ^{31} -$</tex></formula>1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a <formula formulatype="inline"> <tex Notation="TeX">$4.9\times 5.2~{\hbox{mm}}^2$</tex></formula> die. </para>