Crosstalk Analysis Method of 3-D Solenoid On-chip Inductors for High-speed CMOS SoCs

Abstract

A crosstalk between miniaturized "3-D solenoid" on-chip inductors with multi-layered local interconnects is analyzed by an equivalent circuit model using the mixed-mode S-parameters. The circuit model parameters indicate that the crosstalk between the miniaturized 3-D solenoid inductors is originated mainly from the magnetic coupling. Thus, the crosstalk is reduced by arranging guard rings effectively. Based on this result, a design guideline is derived for fine-pitched placement of the 3-D solenoid inductors to minimize the total chip area of the high-speed logic circuits. Usefulness of the fine-pitched 3-D solenoid inductors is demonstrated in a 39.8 Gb/s D-type flip-flop circuit under 1.0 V supply voltage in 65 nm-node CMOS ULSI.