A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology

Abstract

A 40-Gb/s clock recovery circuit incorporates a quarter-rate phase detector and a multiphase LC oscillator to retime the data and demultiplex it into four 10 Gb/s outputs. Fabricated in 0.18 /spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps RMS and 9.67 ps peak-to-peak while consuming 144 mW.