2005 · 18 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingFault-tolerant SystemsMicroelectronicsBuilt-in Self-testDesign For TestabilityFault InjectionFault ModelingHardware Fault ToleranceReliable System DesignBit Flip Fault ModelsElectromagnetic Fault InjectionFault Injection MethodologyHardware Fault InjectionHardware Fault ModelsSignal PropagationSignal Propagation DelayTiming Faults
The following paper describes a new approach to perform physical fault injection in electronic systems. The approach is settled around a gigahertz transverse electromagnetic (GTEM) cell, which is employed in a controlled process to inject faults in the system under test (SUT). The assumed fault models are delay faults (provoked by signal propagation delay increase in SUT critical paths, thus resulting in de-synchronization between the computed data to be latched and the clock signal) and bit-flips (i.e., corruption of static data stored in memory elements).
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Soft-error detection through software fault-tolerance techniques
Maurizio Rebaudengo, M. Sonza Reorda, Marco Torchiano et al. · 2003 · 144 citations