Bit Flip Fault Models

Bit Flip Fault Models is a fault modeling framework in computer systems that represents the class of hardware-level error injection techniques by characterizing faults as single or multiple bit inversions in storage or transmission media to simulate and analyze the effects of transient hardware faults.

48

Publications

1.4K

Citations

186

Authors

88

Institutions

Publications per year

2017–2026

8

Authors

186

  1. SG
    Seyed Ghassem Miremadi

    Sharif University of Technology, Iran

    3 publications · 87 citations

    3

    h-index

  2. PG
    Pedro Gil

    Universitat Politècnica de València, Spain

    3 publications · 61 citations

    3

    h-index

  3. DG
    Daniel Gil

    Universitat Politècnica de València, Spain

    3 publications · 61 citations

    3

    h-index

  4. JR
    Juan–Carlos Ruiz

    Universitat Politècnica de València, Spain

    3 publications · 61 citations

    3

    h-index

  5. MF
    Mark Frederick Hoemmen

    Sandia National Laboratories, United States

    3 publications · 112 citations

    3

    h-index

1–5 of 186

Venues

  1. IEEE Transactions on Nuclear Science

    4 publications · 211 citations

    4

    h-index

  2. 2

    h-index

  3. IEEE Transactions on Computers

    2 publications · 30 citations

    2

    h-index

  4. Computers & Electrical Engineering

    2 publications · 47 citations

    2

    h-index

  5. Journal of Electronic Testing

    JETTA · 2 publications · 42 citations

    1

    h-index

1–5