Bit Flip Fault Models
Bit Flip Fault Models is a fault modeling framework in computer systems that represents the class of hardware-level error injection techniques by characterizing faults as single or multiple bit inversions in storage or transmission media to simulate and analyze the effects of transient hardware faults.
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1.4K
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186
Authors
88
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2017–2026
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Transient fault models and AVF estimation revisited
Nisha George, Carl Elks, B.W. Johnson et al. · 2010 · 75 citations
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
4 h-index
8 publications
213 citations
Chalmers University of Technology
Gothenburg, Sweden
3 h-index
10 publications
235 citations

Sharif University of Technology
Tehran, Iran
3 h-index
12 publications
348 citations

Vanderbilt University
Nashville, United States
2 h-index
13 publications
799 citations
Universidade Federal do Rio Grande do Sul
Porto Alegre, Brazil
2 h-index
4 publications
178 citations
North Carolina State University
Raleigh, United States
2 h-index
3 publications
184 citations

Centre National de la Recherche Scientifique
Paris, France
2 h-index
5 publications
185 citations

University of Lethbridge
Lethbridge, Canada
2 h-index
3 publications
48 citations
1–8 of 88
4 publications · 211 citations
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2 publications · 58 citations
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2 publications · 30 citations
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2 publications · 47 citations
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JETTA · 2 publications · 42 citations
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