A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Abstract

Nanometer SRAM cannot achieve lower VDDmin due to read-disturb, half-select disturb and write failure. This paper demonstrates quantitative performance advantages of a zigzag 8T-SRAM (Z8T) cell over the decoupled single-ended sensing 8T-SRAM (DS8T) with write-back schemes, which was previously recognized as the most area-efficient cell under large σV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> /VDD conditions. Since Z8T uses only 1T for each decoupled read-port, faster 2T differential sensing (D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> S) can be implemented within the same area as the single-ended DS8T. Thanks to D <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> S, Z8T cell enables much faster R/W speed at VDDmin than DS8T. For the same VDDmin/speed, Z8T reduces the cell area by 15%. The Z8T 32 Kb macro is 14% smaller area and 53% faster than DS8T cells. Three macros were fabricated using foundry provided 65 nm low-power and 90 nm generic processes. The measured VDDmin for a 65 nm 256-row 32 Kb and a 32-row 4 Kb macro are 430 mV and 250 mV respectively. The measured VDDmin for a 90 nm 256-row 64 Kb macro is 230 mV.