Design and development of a multi-die embedded micro wafer level package

Abstract

The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today’s “shrinking” products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore’s Law, the packaging is challenged to integrate and shrink. Chips First or Embedded Chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level. A detailed mechanical and structural analysis of the package in terms of the die thickness, wafer size and warpage is presented. The package format is suitable for stacking multiple die in 3D format and 2D format. The paper also deals with characterization of the materials and the process integration of the multidie wafer level packaging. Initial reliability results of the package are also presented.