Design-in-Reliability Approach for NBTI and Hot-Carrier Degradations in Advanced Nodes

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A practical and accurate Design-in-Reliability methodology has been developed for designs on 90–65-nm technology nodes to quantitatively assess the degradation due to hot carrier and negative bias temperature instability. Simulation capability has been built on top of an existing analog simulator ELDO. Circuits are analyzed using this methodology, illustrating the capabilities of the methodology as well as highlighting the impacts of the two degradation modes. </para>