Correlation of logical failures to a suspect process step

Abstract

Traditional yield enhancement efforts have long relied on memory bitmapping techniques. With the industry marching toward system-on-a-chip technology, the importance of logic products has increased exponentially. This necessitates the development of innovative techniques to perform logic yield enhancement. In this paper the authors present a novel technique that can be used to perform logic yield enhancement. The paper concentrates on logic bitmapping at Texas Instruments. Results obtained from a few production samples of a graphics processor are also presented.