AN OPEN-SOURCE TOOL FOR SYSTEMC TO VERILOG AUTOMATIC TRANSLATION

Abstract

As the complexity of electronic sys- tems increases, new ways for describing these sys- tems are proposed. One actual trend involves the use of system level languages that allows the description of the whole system in a higher abstraction level. This type of methodology helps a designer to obtain an appropriate Hw-Sw partition, where the Sw is compiled to the target platform and the Hw is re- fined to bring it down to a lower level of abstraction in order to be synthesized. This last step usually re- quires the use of a translation tool that from a de- scription of the system in a system level modeling language, converts it to an equivalent one in a stan- dard Hardware Description Language, usually Ver- ilog or VHDL. This works presents a tool that from a SystemC RTL description generates its equivalent Verilog code ready to be synthesized by any stan- dard Verilog Synthesis Tool.