IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1993 · 127 citations · 5 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureInterconnect ArchitectureProgrammable Logic DevicesRouting ArchitectureDigital Logic CircuitsField-programmable Gate Arrays (Fpgas)Hierarchical ExpansionInterconnect DelayInterconnect Delay OptimizationLogic VerificationReconfiguration Of Field-programmable Gate ArraysSystem-level Reconfiguration
The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
5
A Sampler of Circuit Switching Networks
An efficient logic emulation system
M. Butts, J. Batcheller, J. N. Varghese · 1992 · 68 citations