Logic Verification
Logic Verification is a systematic methodology within digital logic design that distinguishes itself by formally ensuring the functional correctness of a logic circuit or system with respect to its intended specification through exhaustive or analytical means.
197
Publications
17.6K
Citations
475
Authors
172
Institutions
Publications per year
2017–2026
11
Parents
197
Graph-Based Algorithms for Boolean Function Manipulation
Bryant · IEEE Transactions on Computers · 1986 · 8.9K citations · Full text
Logic verification using binary decision diagrams in a logic synthesis environment
Sharad Malik, A.R. Wang, Robert K. Brayton et al. · 2003 · 509 citations
Leslie Lamport · IFIP Congress · 1983 · 445 citations
Chris Hawblitzel, Jon Howell, Manos Kapritsos et al. · 2015 · 309 citations
1–5 of 197
475
University of California, Berkeley, United States
5 publications · 642 citations
5
h-index
5
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4
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4
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4
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1–5 of 475
172
University of California, Berkeley
Berkeley, United States
10 h-index
24 publications
3.1K citations
Synopsys (United States)
Mountain View, United States
7 h-index
9 publications
481 citations
University of Southern California
Los Angeles, United States
6 h-index
10 publications
767 citations
Carnegie Mellon University
Pittsburgh, United States
6 h-index
10 publications
9.3K citations
University of Arizona
Tucson, United States
5 h-index
6 publications
404 citations
Stanford University
Stanford, United States
5 h-index
6 publications
356 citations
University of Michigan
Ann Arbor, United States
5 h-index
9 publications
336 citations

Imperial College London
London, United Kingdom
4 h-index
10 publications
289 citations
1–8 of 172
11 publications · 652 citations
11
h-index
Conference · 8 publications · 166 citations
8
h-index
5 publications · 9.1K citations
5
h-index
3 publications · 129 citations
3
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TSE · 3 publications · 123 citations
3
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1–5