Logic Verification

Logic Verification is a systematic methodology within digital logic design that distinguishes itself by formally ensuring the functional correctness of a logic circuit or system with respect to its intended specification through exhaustive or analytical means.

197

Publications

17.6K

Citations

475

Authors

172

Institutions

Publications per year

2017–2026

11

Authors

475

  1. AS
    Alberto Sangiovanni‐Vincentelli

    University of California, Berkeley, United States

    5 publications · 642 citations

    5

    h-index

  2. RK
    Robert K. Brayton

    University of California, Berkeley, United States

    5 publications · 755 citations

    5

    h-index

  3. ND
    Neil Daeche

    University of Kent, United Kingdom

    4 publications · 106 citations

    4

    h-index

  4. RD
    Rolf Drechsler

    University of Bremen, Germany

    4 publications · 139 citations

    4

    h-index

  5. YL
    Yung-Te Lai

    University of Southern California, United States

    4 publications · 360 citations

    4

    h-index

1–5 of 475

Venues

  1. 11

    h-index

  2. Design Automation Conference

    Conference · 8 publications · 166 citations

    8

    h-index

  3. IEEE Transactions on Computers

    5 publications · 9.1K citations

    5

    h-index

  4. Computer

    3 publications · 129 citations

    3

    h-index

  5. IEEE Transactions on Software Engineering

    TSE · 3 publications · 123 citations

    3

    h-index

1–5