2011 · 17 citations · 3 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsLow-noise Circuit DesignMixed-signal Integrated Circuit DesignAnalog-digital ConversionCmos Analog Circuit DesignCmos Analog Integrated CircuitsLow-noise Analog InterfacesLow-power Latch DesignRf Cmos DesignSiliconSingle-supply Operation
A 9b 3GS/s pure binary current steering DAC is implemented in 65nm CMOS. It demonstrates a low noise CML latch and a low power delay balancing technique while drawing 50mA from a single 1.2V power supply. When sampling at 3GHz, it exhibits more than 50dB SFDR until 1.5GHz output frequency and less than −60dB IM3 up to 1GHz output frequency. Total silicon area is less than 0.04mm2.
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A 12b 500MS/s DAC with <70dB SFDR up to 120MHz in 0.18μm CMOS
Kostas Doris, J. Briaire, D.M.W. Leenaerts et al. · 2005 · 51 citations