2005 · 51 citations · 4 references
EngineeringElectrical EngineeringAnalog ElectronicsCircuit TheoryMicroelectronicsAnalog Integrated CircuitsAnalog IntegrationCmos Circuit DesignMixed-signal Integrated Circuit DesignMixed-signal IntegrationNoise In Analog CircuitsAnalog-to-digital Converter DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsCurrent SteeringOutput ImpedancePerformance DegradationPower Supply NoiseSettling
A Nyquist high-linearity 12b 500MS/s current steering (CS) DAC implemented in a 0.18μm 1.8V CMOS process and intended for multi-carrier communication applications is presented. To satisfy linearity requirements at low frequencies, the output resistance and the mismatch between current sources are of primary concern. Linearity at high frequencies is often limited by low, output impedance, nonlinear settling, charge feedthrough, major carry glitches and spikes in common switch nodes. Timing errors due to mismatch or clock skew, power supply noise, and substrate noise may also significantly degrade performance. Several of these nonlinearities and timing errors have been tackled in recent designs [1-3] and correction circuitry was required to reach a state-of-the-art performance [2,3]. In this work, attention is paid to all these errors, and in particular to timing errors, supply and bias disturbances. The aim is to avoid the generation of non-linearity and therefore no attempt is made to suppress it in the output signal [2,3].
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