A 12b 2.9GS/s DAC with IM3 ≪−60dBc beyond 1GHz in 65nm CMOS

Abstract

A 12 b 2.9 GS/S current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 <-60 dBc beyond 1 GHz while driving a 50 Omega load with an output swing of 2.5 V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp-diff</sub> and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/S is better than 60 dB beyond 340 MHz.