2004 · 209 citations · 8 references
EngineeringComputer EngineeringComputer ArchitectureDesign OptimizationInterconnection NetworksDesign Space ExplorationInterconnect ArchitectureNetwork-on-chip DesignPower-aware DesignRoutingRouting ArchitectureArchitectural ExplorationArchitecture ExplorationExplorationNetwork-on-chipNetwork-on-chip ArchitecturesOn-chip NetworksPower ConsumptionPower Consumption Optimization
In this paper we present an approach to multi-objective exploration of the mapping space of a mesh-based network-on-chip architecture. Based on evolutionary computing techniques, the approach is an efficient and accurate way to obtain the Pareto mappings that optimize performance and power consumption. Integration of the approach in an exploration framework with a kernel based on an event-driven trace-based simulator makes it possible to take account of important dynamic effects that have a great impact on mapping. Validation on both synthesized traffic and real applications (an MPEG-2 encoder/decoder system) confirms the efficiency, accuracy and scalability of the approach.
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William J. Dally, Brian Towles · 2001 · 3.2K citations
Engineering, Computer Engineering, Electrical Engineering +17
Getting to the bottom of deep submicron
Dennis Sylvester, Kurt Keutzer · 1998 · 283 citations