Maurizio Palesi - Concepedia

Author

Maurizio Palesi

Also Known As

Cardellini, Valeria, Daniela Panno, M Palesi, M. Palesi, MAURIZIO PALESI, Maurizio Palesi, Palesi, Maurizio, Vincenzo Catania

241

Publications

3.9K

Citations

H-Index

Concepts

All Affiliations

University of Catania Università degli Studi di Enna Kore Jönköping University Guangdong University of Finance Sun Yat-sen University

About

Maurizio Palesi is an author at University of Catania specializing in engineering, computer engineering, and computer architecture.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	29	66	3.1K
2	Computer Engineering	29	65	3.1K
3	Computer Science	24	42	2.2K
4	Natural Sciences	1	1	16
5	Social Sciences	1	1	25

Maurizio Palesi

Publications

3.2K

Citations

H-Index

Page 1

	Year	Citations
Noxim: An open, extensible and cycle-accurate network on chip simulator Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Winoc ArchitecturesEngineeringComputer ArchitectureInterconnection Network ArchitectureHigh-performance Architecture	2015	294
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi, IEEE Transactions on Computers EngineeringNetwork RoutingComputer ArchitectureAdaptive RoutingInterconnection Network Architecture	2008	236
Cycle-Accurate Network on Chip Simulation with Noxim Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, ACM Transactions on Modeling and Computer Simulation System On ChipChip SimulationWinoc ArchitecturesEngineeringEdge Computing	2016	213
Multi-objective mapping for mesh-based NoC architectures Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi EngineeringEvolvable HardwareComputer ArchitectureComputer-aided DesignMulti-objective Exploration	2004	209
Multi-objective design space exploration using genetic algorithms Maurizio Palesi, Tony Givargis Design Space ExplorationComputational ScienceEngineeringGenetic AlgorithmsSoc Architecture	2002	186
Application Specific Routing Algorithms for Networks on Chip Maurizio Palesi, Rickard Holsmark, Shashi Kumar, IEEE Transactions on Parallel and Distributed Systems Homogeneous Mesh NocNetwork Routing AlgorithmEngineeringNoc PlatformEdge Computing	2009	170
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, EngineeringNetwork RoutingComputer ArchitectureNetwork AnalysisInterconnection Network Architecture	2012	93
Efficient design space exploration for application specific systems-on-a-chip Giuseppe Ascia, Vincenzo Catania, Alessandro Di Nuovo, Journal of Systems Architecture Design Space ExplorationSystem On ChipEngineeringComputer DesignDesign	2007	92
A methodology for design of application specific deadlock-free routing algorithms for NoC systems Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Network Routing AlgorithmEngineeringDeadlock Free RoutingEdge ComputingRouter Architecture	2006	88
An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators Seyed Morteza Nabavinejad, Mohammad Baharloo, Kun-Chih Chen, IEEE Journal on Emerging and Selected Topics in Circuits and Systems EngineeringMachine LearningHardware AlgorithmComputer ArchitectureInterconnection Network Architecture	2020	74

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