Circuit aging prediction for low-power operation

Abstract

Low-power circuit operations, such as dynamic voltage scaling and the sleep mode, pose a unique challenge to aging prediction. Traditional aging models assume constant voltage and averaged activity factor, ignoring the impact of the long sleep period, and thus, result in a significant overestimation of the degradation rate. To accurately predict the aging effect in low-power design, this work first examines critical model assumptions in the reaction-diffusion process that is responsible for the NBTI effect. By using the correct diffusion profile, it then proposes a new aging model that effectively analyzes the degradation under various low-power operations. The new model well predicts the aging behavior of scaled CMOS measurement data (45 nm and 65 nm) with different operation patterns, especially sleep mode operation and dynamic voltage scaling. Compared to previous aging models, the new result captures the essential role of the long recovery phase in circuit aging, reducing unnecessary guardbanding in reliability protection.