IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2001 · 271 citations · 11 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSemiconductor DevicesCmos Circuit DesignIntegrated Circuit DesignNoiseNoise ReductionNoise Reduction DesignPower OptimizationCurrent NoiseLow-noise AmplificationLow-noise AmplifiersNoise AnalysisNoise Figure OptimizationNoise In AmplifiersNoise OptimizationPower Consumption
This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels.
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A physics-based MOSFET noise model for circuit simulators
Kuo-Hsiang Hung, P.K. Ko, Chenming Hu et al. · IEEE Transactions on Electron Devices · 1990 · 256 citations
The Design of CMOS Radio-Frequency Integrated Circuits
Brian Ellis · Circuit World · 2004 · 181 citations
Engineering, Computer Engineering, Electrical Engineering +12