Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner

Concepts

EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsMicroelectronicsSemiconductor DevicesMetal-oxide-semiconductor Field-effect TransistorsStrain AnalysisStrain EngineeringStrain HardeningStress-strain BehaviorThin Film StrainGate Oxide DegradationSource-drain EngineeringStrain EffectsStrain Effects On Electronic PropertiesStrain-softening EffectsStress Engineering In Thin FilmsStress In Nanostructures

Abstract

We report the demonstration of 25-nm gate-length L G strained nMOSFETs featuring the silicon-carbon source and drain (Si 1-y C y S/D) regions and a thin-body thickness T body of ~18 nm. This is also the smallest reported planar nMOSFET with the Si 1-y C y S/D stressors. Strain-induced mobility enhancement due to the Si 1-y C y S/D leads to a significant drive-current I Dsat enhancement of 52% over the control transistor. Furthermore, the integration of tensile-stress SiN etch stop layer and Si 1-y C y S/D extends the I Dsat enhancement to 67%. The performance enhancement was achieved for the devices with similar subthreshold swing and drain-induced barrier lowering. The Si 1-y C y S/D technology and its combination with the existing strained-silicon techniques are promising for the future high-performance CMOS applications

References

A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors

T. Ghani, M Armstrong, C. Auth et al. · 2004 · 561 citations

Engineering, Computer Engineering, Electrical Engineering +17

Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design

Seiichi Ito, Hironao Namba, Keiko Yamaguchi et al. · 2002 · 153 citations

Engineering, Electrical Engineering, Materials Science +17

In-plane mobility anisotropy and universality under uni-axial strains in n- and p-MOS inversion layers on [100], [110], and [111] Si

Hiroshi Irie, Koji Kita, Kentaro Kyuno et al. · 2005 · 109 citations

Engineering, Materials Engineering, Materials Science +13

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

Chenjun Ge, Cheng Lin, C.H. Ko et al. · 2004 · 109 citations

Engineering, Electrical Engineering, Low-power Design +11

A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

S. Pidin, Toshihiko Mori, K. Inoue et al. · 2005 · 105 citations

Engineering, Electrical Engineering, Materials Science +17