IEEE Transactions on Electron Devices · 2007 · 13 citations · 8 references
EngineeringMaterials EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsMemory DevicesNanomechanicsStrain EngineeringData RetentionFloating-gate MemoryNonvolatile MemoryRetention CharacteristicsSilicon NitrideStrain EffectsTensile StrainTensile Strength
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Experimental data show that tensile stress improves and compressive stress degrades retention time for nonvolatile memory (NVM) devices. External mechanical tensile stress and compressive stress are introduced into the NVM floating-gate and nitride trap based memories via four-point wafer bending. The enhanced retention time under tensile stress results from stress-altered changes in the <formula formulatype="inline"><tex>$\hbox{SiO}_{2}/\hbox{Si}$</tex> </formula> barrier height and out-of-plane conductivity mass for floating-gate memories and from changes in the trap activation energy in nitride based memories. </para>
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Analysis and modeling of floating-gate EEPROM cells
Avinoam Kolodny, S. T. K. Nieh, B. Eitan et al. · IEEE Transactions on Electron Devices · 1986 · 178 citations
Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing
Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations
Engineering, Electrical Engineering, Manufacturing Engineering +11