The Effect of Field Oxide Recess on Cell $V_{\rm TH}$ Distribution of nand Flash Cell Arrays

Abstract

We present our study on the effect of field oxide recess on cell-programming-speed uniformity of nand flash cell memory. Due to the short distance between the control gate and the shallow-trench-isolation (STI) edge, the control-gate voltage generates uniform distribution of an electric field on the STI edge and provides strong immunity to fabrication process variation in cell programming. Therefore, the optimized field oxide recess offers an inherently narrower cell <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> distribution, fastening multilevel-cell programming speed while minimizing the floating-gate interference. Experimental results on 63-nm cell arrays show that the cell <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> distribution is reduced by 18% or more as field oxide recess increases.