A VLSI FSM Design System

Abstract

This paper describes a fully automated finite-state machine (FSM) synthesis system. The FSM is realized as a PLA. This synthesizer accepts a high-level description of the FSM and generates a mask level layout. Several simulation models are produced at different levels of abstraction; these models can be integrated with other modules on the chip to aid in the debugging of the overall VLSI chip design. Valuable information on speed, area, and testability of the PLA can be obtained through a collection of audit programs. This system has been used to design complex controllers for many VLSI chips at AT & T Bell Laboratories. Although a PLA implementation is assumed, the system can be extended to synthesize a random logic implementation of the FSM.