Concepedia

Mask Layout Generation

Mask Layout Generation is a method in semiconductor manufacturing that translates circuit design specifications into geometric patterns defining photomasks used for patterning layers during integrated circuit fabrication.

93

Publications

2.4K

Citations

329

Authors

82

Institutions

Publications per year

2017–2026

5

Parents

Publications

93

A Discrete Fourier-Cosine Transform Chip

Martin Vetterli, A. Ligtenberg · IEEE Journal on Selected Areas in Communications · 1986 · 111 citations · Full text

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<title>Automated optical proximity correction: a rules-based approach</title>

O.W. Otto, Joseph G. Garofalo, Kevin Low et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 1994 · 81 citations

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70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

Woo Young Choi, Jae Young Song, Jong Duk Lee et al. · 2005 · 79 citations

, , +15

Design of digital camouflage by recursive overlapping of pattern templates

Feng Xue, Shan Xu, Yuetong Luo et al. · Neurocomputing · 2015 · 65 citations

, , +16

Direct projection on dry-film photoresist (DP2): do-it-yourself three-dimensional polymer microfluidics

Siwei Zhao, Hailin Cong, Tingrui Pan · Lab on a Chip · 2009 · 62 citations

, , +17

1–5 of 93

Authors

329

  1. EK
    Erik K. Antonsson

    California Institute of Technology, United States

    6 publications · 108 citations

    6

    h-index

  2. BP
    Bryan Preas

    Palo Alto Research Center, United States

    4 publications · 160 citations

    4

    h-index

  3. CW
    C. W. Gwyn

    Sandia National Laboratories California, United States

    4 publications · 125 citations

    4

    h-index

  4. LP
    Linyong Pang

    Luminex (United States), United States

    3 publications · 77 citations

    3

    h-index

  5. RP
    R. P. Larsen

    Argonne National Laboratory, United States

    2 publications · 35 citations

    2

    h-index

1–5 of 329

Institutions

82

  1. University of California, Berkeley

    Berkeley, United States

    5 h-index

    12 publications

    228 citations

  2. Sandia National Laboratories California

    Livermore, United States

    4 h-index

    16 publications

    287 citations

  3. Luminex (United States)

    Austin, United States

    4 h-index

    17 publications

    370 citations

  4. California Institute of Technology

    Pasadena, United States

    4 h-index

    6 publications

    111 citations

  5. Massachusetts Institute of Technology

    Cambridge, United States

    3 h-index

    8 publications

    332 citations

  6. University of California, Los Angeles

    Los Angeles, United States

    3 h-index

    5 publications

    189 citations

  7. NEC (Japan)

    Tokyo, Japan

    2 h-index

    13 publications

    274 citations

  8. University of Edinburgh

    Edinburgh, United Kingdom

    2 h-index

    4 publications

    78 citations

1–8 of 82

Venues

  1. 13

    h-index

  2. Design Automation Conference

    Conference · 7 publications · 147 citations

    7

    h-index

  3. 3

    h-index

  4. Journal of Micromechanics and Microengineering

    JMM · 3 publications · 76 citations

    3

    h-index

  5. TechConnect Briefs

    3 publications · 52 citations

    3

    h-index

1–5