Static-Noise-Margin Analysis of Conventional 6T SRAM Cell at 45nm Technology

Abstract

Static random access memory (SRAM) is a type of volatile semiconductor memory to store binary logic '1 ' and '0'. The SRAM sizing has been scaled down due to the increase density of SRAM in System-On-Chip (SoC) and other integrated devices, which works on lower supply voltage. This leads to considerable amount of power saving, but the stability and performance of the SRAM circuit is also being affected due to the scaling of supply voltage. The lower supply voltage reduces the Static Noise Margin upon which the stability of the SRAM cell depends. With lower Vdd, the delay of SRAM cell increases considerably and speed of the SRAM will be lowered. This paper discusses about the noise effect on Read SNM and Write SNM of Conventional 6T SRAM cell. This paper also presents the effect of device parameters on Conventional 6T SRAM cell which increases the cell stability without increasing transistor count at 45nm technology.