IEEE Journal of Solid-State Circuits · 1992 · 31 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignClock ManagementCmos Circuit DesignDigital Integrated Circuit DesignLow-power Digital Circuit DesignProgrammable Logic DevicesTiming AnalysisCmos Digital Circuit DesignCmos Logic CircuitsCmos Logic DesignDynamic Power DissipationHigh-speed Circuit DesignHigh-speed Cmos DesignProgrammable Logic ArrayStatic Power Dissipation
The circuit implementation of a CMOS programmable logic array (PLA) is described for use with a single-phased clock, combining both dynamic and pseudo-NMOS design styles. Compact layout and high speed of operation is achieved with low static power dissipation. The circuit design, circuit speed, circuit layout, and timing diagram are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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