G.M. Blair

Low-power double-edge triggered flipflop

G.M. Blair · Electronics Letters · 1997 · 41 citations

Engineering, Computer Engineering, Electrical Engineering +17

Designing low-power digital CMOS

G.M. Blair · Electronics & Communications Engineering Journal · 1994 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +16

PLA design for single-clock CMOS

G.M. Blair · IEEE Journal of Solid-State Circuits · 1992 · 31 citations

Engineering, Computer Engineering, Electrical Engineering +17

Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"

G.M. Blair · IEEE Journal of Solid-State Circuits · 1997 · 26 citations

Engineering, Computer Engineering, Electrical Engineering +15

Low cost sorting circuit for VLSI

G.M. Blair · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 1996 · 25 citations

Engineering, Computer Engineering, Computer Science +13