Re-examination of indium implantation for a low power 0.1 μm technology

Abstract

The use of indium for NMOS channel doping in a 0.1 /spl mu/m CMOS technology is fully re-considered. For the first time, we clearly demonstrate that the room temperature carrier freeze-out is responsible for large discrepancies between spreading resistance and SIMS measurements but that it does not affect Indium doped NMOSFET's operation. 0.1 /spl mu/m NMOS transistors have been fabricated using Indium for channel doping. A strong reduction in short channel effect and a slight improvement in the effective low-field mobility have been obtained.