Applicability limits of the two-frequency capacitance measurement technique for the thickness extraction of ultrathin gate oxide

Abstract

Reliable techniques for extracting the gate dielectric layer thickness from capacitance-voltage (C-V) characteristics are essential for manufacturing process quality control. Continued reduction of the dielectric layer thickness has brought about a need for new measurement procedures which can account for the direct tunneling currents through the gate insulator. We present a guideline for performing two-frequency C-V analysis of sub-2 nm gate oxides and show that it is possible to extract the dielectric layer thickness with an error of less than 4%. We show that in order to achieve this level of accuracy, it is necessary to choose the measurement frequencies and the test device size so that the dissipation remains below 1.1 at least at one of the two measurement frequencies.