Fabrication technologies for three-dimensional integrated circuits

TLDR

The MIT approach to 3D VLSI integration relies on low‑temperature Cu‑Cu wafer bonding, with key reliability criteria including structural integrity, electrical characteristics, process flow efficiency, and the need for CAD tools to aid design and layout. The paper reports recent results on the MIT 3D VLSI integration approach, covering reliability criteria and CAD tool development. Device wafers are bonded face‑to‑back using short vertical vias and Cu‑Cu pads as inter‑wafer throughways.

Abstract

The MIT approach to 3D VLSI integration is based on low-temperature Cu-Cu wafer bonding. Device wafers are bonded in a face-to-back manner, with short vertical vias and Cu-Cu pads as the inter-wafer throughway. In our scheme, there are several reliability criteria, which include: (a) structural integrity of the Cu-Cu bond; (b) Cu-Cu contact electrical characteristics; and (c) process flow efficiency and repeatability. In addition, CAD tools are needed to aid in design and layout of 3DICs. This paper discusses recent results in all these areas.