Statistical prediction of circuit aging under process variations

Abstract

Accurate prediction of circuit aging and its variability is essential to reliable design and analysis. Such a capability further helps reduce the load in statistical reliability test. Based on compact models of transistor degradation and circuit performance, we develop analytical solutions that efficiently predict the statistics of both circuit timing and the leakage under temporal stress and process variations. These solutions prove that circuit aging and its variance can be fully predicted from the characteristics of transistor degradation and circuit performance sensitivity to aged parameters, independent on the type and the amount of process variations. Specific results include: (1) under variations, the standard deviation of circuit speed declines with the stress time, following a power law of 1/6; and (2) the logarithmic mean and the standard deviation of leakage current decrease with the stress time as t <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1/6</sup> . The results are systematically validated by simulation and measurement data from an industrial 65nm technology, enhancing the predictability and efficiency of statistical reliability analysis.