Investigation and Localization of the SiGe Source/Drain (S/D) Strain-Induced Defects in PMOSFET With 45-nm CMOS Technology

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this letter, for the first time, the defects that are induced from the SiGe strain source/drain (S/D) in PMOSFET with 45-nm CMOS technology were investigated in detail. With the conventional charge pumping and the improved low gate-leakage gated-diode <formula formulatype="inline"><tex>$(\hbox{L}^{2}$</tex></formula>– <formula formulatype="inline"><tex>$\hbox{GD})$</tex></formula> measurements, we find that the uniaxial compressive stress from SiGe S/D generates a large number of acceptorlike interface states at the gate oxide/extension of S/D interface, thus enhancing the leakage current. Compared to defects that are caused by the relaxed <formula formulatype="inline"><tex>$\hbox{Si}_{1-x}\hbox{Ge}_{x}$</tex></formula> on the conventional graded <formula formulatype="inline"><tex>$\hbox{Si}_{1-x}\hbox{Ge}_{x}$</tex></formula> buffer layer, the SiGe S/D experienced results that are more serious. The acceptorlike interface states are suspected to be the Si dangling bonds broken by the stress. A schematic model is proposed to illustrate the effect of the stress comprehensively. </para>