Asia and South Pacific Design Automation Conference · 2009 · 16 citations · 23 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDevice CharacterizationDevice ModelingDevice ReliabilityDevice SimulationLeakage Power ReductionSemiconductor ReliabilityGate LeakageLeakage Current AnalysisLeakage Current ModelingLeakage PowerLeakage Power EstimationPower Analysis Of Microarchitectural LeakageTransistor-level Leakage Analysis
In this paper, we present a novel statistical full-chip leakage power analysis method. The new method can provide a general framework to derive the full-chip leakage current or power in a closed form in terms of the variational parameters, such as the channel length, the gate oxide thickness, etc. It can accommodate various spatial correlations. The new method employs the orthogonal polynomials to represent the variational gate leakages in a closed form first, which is generated by a fast multi-dimensional Gaussian quadrature method. The total leakage currents then are computed by simply summing up the resulting orthogonal polynomials (their coefficients). Unlike many existing approaches, no grid-based partitioning and approximation are required. Instead, the spatial correlations are naturally handled by orthogonal decompositions. The proposed method is very efficient and it becomes linear in the presence of strong spatial correlations. Experimental results show that the proposed method is about 10× faster than the recently proposed method [4] with constant better accuracy.
23
Numerical recipes in C: the art of scientific computing
Choice Reviews Online · 1993 · 18.1K citations · Full text
Numerical recipes in Pascal: the art of scientific computing
Choice Reviews Online · 1990 · 11.9K citations