2006 · 28 citations · 11 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignHardware AccelerationInstruction Set ArchitectureLow-power Fpga DesignProcessor Core DesignRegister-transfer Level DesignTiming AnalysisData PipeliningData PrefetchingHardware PipeliningLow-latency DesignPipeliningPrefetchingPrefetching StrategiesSpeculative Prefetching
This paper presents an innovative hardware implementation of the H.264/AVC CABAC binary arithmetic decoder and context modeler capable of decoding one symbol per clock cycle at high clock frequencies while maintaining a slim hardware footprint. This was achieved by substantially decreasing the latency of the central feedback loop through extensive use of speculative prefetching and aggressive pipelining. Actual synthesis results targeted at the state-of-the-art FPGA families show that our approach results in a fast and compact IP core, ideal for a SoC H.264/AVC implementation
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Video coding with H.264/AVC: tools, performance, and complexity
Jörn Östermann, J. Bormans, Peter List et al. · IEEE Circuits and Systems Magazine · 2004 · 899 citations