Heterogeneous routing architecture for low-power FPGA fabric

Abstract

In this study, we present design techniques to implement low power FPGA routing architecture by combining fast and slow routing resources, where the circuit design of slow resource is optimized to reduce leakage power. Timing-driven placement and routing experiments along with power modeling are used to identify the type and percentage of resources that can be slowed down. Based on our analysis, we present a heterogeneous (HT) routing architecture to reduce standby power dissipation of FPGA routing fabric by 33% without any area penalty and at the cost of less than 5% performance degradation.