EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsVlsi DesignCmos Circuit DesignDigital Logic DesignDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementPower OptimizationAdiabatic LogicCarry-lookahead LogicCmos Logic CircuitsLow-power Circuit DesignLow-power Logic DesignStatic Cmos LogicThreshold VoltageThroughput
Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power range with a practical loading and operation frequency range. Circuits are designed using 1.0 /spl mu/m CMOS technology with a reduced threshold voltage of 0.2 V.
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Cascode voltage switch logic: A differential CMOS logic family
L.G. Heller, W. Paul Griffin, Jack Davis et al. · 1984 · 482 citations
Engineering, Computer Engineering, Electrical Engineering +14
Adiabatic Computing with the 2n-2n2d Logic Family
Andreas Krämer, J. S. Denker, Stephen Avery et al. · 2005 · 116 citations