2002 · 20 citations · 8 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsDigital Logic DesignDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementPower OptimizationPower-aware DesignLatch DesignLogic Family DesignLow-power Flip-flop DesignLow-power Latch DesignLow-power Logic DesignPower-efficient Logic Block DesignThreshold CircuitsThreshold Logic
This paper presents a new low-power threshold logic family with self lock-out property. The simulated results have shown that, the proposed threshold logic dissipates between 10% and 79% less power and between 57% and 71% less energy, at V/sub DD/=5 V, when compared with previous similar threshold logic families. Moreover, at V/sub DD/=3.3 V, it has between 12% and 48% less energy and between 34% and 60% less dissipated power in the worst case.
8
Neural computation of arithmetic functions
K.-Y. Siu, Jehoshua Bruck · Proceedings of the IEEE · 1990 · 64 citations
Low-power CMOS threshold-logic gate
M.J. Avedillo, J.M. Quintana, A. Rueda et al. · Electronics Letters · 1995 · 47 citations
Engineering, Computer Engineering, Electrical Engineering +17