IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 32 citations · 12 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureField-programmable Gate ArraysLow-power DesignConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitecturePower EstimationPower ManagementPower OptimizationDynamic Power EstimationField-programmable Gate Array Power EstimationField-programmable Gate Arrays (Fpgas)Multiplier DesignMultipliersPower ConsumptionPower ModelPower Modeling And Estimation
The use of embedded multiplier blocks has become a norm in DSP applications due to their high performance and low power consumption. However, as their implementation details in commercial field-programmable gate arrays are not available to users, and the power estimates given by the tested low-level tool are not accurate enough to validate high-level models, the work on power estimation of these blocks is very limited. We present a dynamic power estimation methodology for the embedded multipliers in Xilinx Virtex-II Pro chips. The methodology is an adaptation of an existing power estimation method for lookup-table-based components and uses information about the type of architecture of the embedded block. The power model is characterized and verified by on-board measurements and is ready for integration with high-level power optimization techniques. The experimental results show that the average accuracy of the model is higher than the average accuracy of the low-level commercial tool.
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Dynamic power consumption in Virtex™-II FPGA family
Li Shang, Alireza Kaviani, Kusuma Bathala · 2002 · 393 citations