IEEE Design & Test of Computers · 1998 · 110 citations · 4 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureLookup TablesProgrammable Logic DevicesRoutingClustered Logic Block ArchitectureFlexibilityLogic Block DesignLogic Element DesignLookup Table DesignLut ClusteringReconfigurable Logic BlocksRouting In Field-programmable Gate Arrays
The logic blocks of most FPGAs contain clusters of lookup tables and flip-flops yet little is known about good choices for key parameters. How many lookup tables should a cluster contain, how should FPGA routing flexibility change as cluster size changes, and how many inputs should programmable routing provide each cluster?.
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