LUT Clustering is a computational optimization technique that belongs to the class of logic synthesis methods, specifically distinguished by its strategy of grouping multiple Lookup Tables (LUTs) into clusters to minimize area and delay in FPGA-based circuit designs.
18
Publications
1K
Citations
41
Authors
19
Institutions
Publications per year
2017–2026
1
Parents
Publications
18
1–5 of 18
Authors
41
- JR
4
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- MS
3
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- EB
2
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- SO
2
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- WF
2
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1–5 of 41
Institutions
19
University of Toronto
Toronto, Canada
4 h-index
8 publications
1.4K citations
Northwestern University
Evanston, United States
3 h-index
3 publications
133 citations
University of California, Los Angeles
Los Angeles, United States
3 h-index
5 publications
231 citations
Intel (United States)
Santa Clara, United States
2 h-index
3 publications
55 citations
École Polytechnique Fédérale de Lausanne
Lausanne, Switzerland
2 h-index
6 publications
110 citations
Istituto Nazionale di Fisica Nucleare, Laboratori Nazionali di Frascati
Frascati, Italy
1 h-index
2 publications
22 citations
Chinese Academy of Sciences
Beijing, China
1 h-index
3 publications
66 citations
University of Colorado Boulder
Boulder, United States
1 h-index
2 publications
28 citations
1–8 of 19
Venues
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems
2 publications · 441 citations
2
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- Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment
1 publications · 11 citations
1
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- IEEE Design & Test of Computers
1 publications · 110 citations
1
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- Journal of Circuits Systems and Computers
JCSC · 1 publications · 47 citations
1
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- Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
Conference · 1 publications · 22 citations
1
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