IEEE Journal of Solid-State Circuits · 1992 · 12 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsFault-tolerant ComputingMicroelectronicsBuilt-in Self-testCmos Circuit DesignDesign For TestabilityAnalog Built-in Self-testAnalog TestabilityArea Overhead AnalysisBuilt-in Self-test For Analog CircuitsCmos Analog Circuit DesignCmos Analog Integrated CircuitsDesign For Testability CheckingTestability
A design-for-testability scheme for detecting CMOS analog faults was reported by Favalli et al. (see ibid., vol.25, no.5, p.1239-46, 1990). The authors propose two alternative designs, one for small circuits and another for large circuits, which require significantly less area overhead (about 1/4 to 1/3) than that of Favalli's design. With the proposed modification in the first design, the untestable problem, which occurred in Favalli's design, can be alleviated. Furthermore, the proposed schemes are also fit to be implemented in VLSI circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Novel design for testability schemes for CMOS ICs
M. Favalli, P. Olivo, M. Damiani et al. · IEEE Journal of Solid-State Circuits · 1990 · 47 citations
Engineering, Computer Engineering, Electrical Engineering +16