Manufacturable Processes for $\leq$ 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Abstract

Manufacturable processes to reduce both channel and external resistances (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ext</sub> ) in CMOS devices are described. Simulations show that R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ext</sub> will become equivalent to strained Si channel resistance near the 32-nm logic node. Tensile stress in plasma-enhanced chemical-vapor-deposited SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> liners is increased with UV curing, boosting the NMOS drive current by 20% relative to a neutral reference. W contact-plug resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) is reduced by 40% by optimizing preclean, liner/barrier, and nucleation steps. Replacing the fill material with Cu reduces R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> by > 35% as compared to W. The Schottky barrier height of silicide contacts to p-Si is reduced by 0.12 eV with a 10% addition of Pt, resulting in a ~10% increase in the PMOS drive current. By implementing a two-step anneal process (spike + laser), the source/drain-extension resistance can be reduced by 20%.