IEEE Transactions on Circuits and Systems I Regular Papers · 2010 · 32 citations · 39 references
EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesCmos Circuit DesignDevice CharacterizationElectrostatic Discharge ProtectionIntegrated Circuit DesignInterconnect DesignInterconnect TechnologyCharged Device ModelDevice Scaling EffectsElectrostatic DischargeHigh-speed Cmos DesignHigh-speed I/o Circuit DesignMetal Interconnect ScalingPackaging For High-frequency DevicesSilicon
Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies are addressed by improving design, characterization, and modeling of I/O MOSFETs, interconnect, ESD protection and power clamp devices. Recent progress on ESD protection design for both high-speed digital I/O and radiofrequency (RF) circuits are presented. Topological trade-offs are compared. High speed circuit protection techniques such as the T-coil based ESD design are reviewed in detail. Package- and wafer-level charged device model (CDM) correlation issues are discussed. I/O, ESD devices, and metal interconnect effects are examined using very fast transmission line pulses (VF-TLP) and TLP.
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