IEEE Transactions on Electron Devices · 2009 · 45 citations · 31 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsAmorphous SemiconductorsDevice CharacterizationDevice ModelingDevice ReliabilitySemiconductor ReliabilityThin-film TransistorsAmorphous SiliconAmorphous Silicon Thin-film TransistorsHumidityNegative Bias Temperature InstabilityReliability DegradationReliability Degradation MechanismsThin-film Transistor ModelingWear-out Mechanisms
This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.
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